Re: [Sheflug] c++ & mem

["Alex Hudson" <nospam [at] alexhudson.com>]

> > I really don't see why a compiler can't unroll a loop? That's not
exactly
> > hard. I'm not really sure what the hardware data sheet has to do with
> > things, either.
>
> Determining when and by how much do so is hard, as inappropriate loop
unrolling
> may decrease performance by increasing cache misses. It is therefore
nessercary
> to know something about cache beahvour to make an appropriate decision.
This
> not not to say that a complier can't do better than a programmer writing
in a
> high level language, who may not know which processor is going to be used
to
> execute the code.

It's possibly appropriate to know something about the size of the
instruction cache for a 'maximum ceiling' type thing, but I would have
thought the main problem would be that programmer / compiler wouldn't know
what was in the cache anyway, wouldn't know when they were going to be
swapped out, etc., and would expect a fair number of instruction cache
misses anyway. From what I recall from architectures class, larger
instruction caches generate more misses, but these are generally cancelled
out anyway because of the positive effects of pipelining / look aheads that
modern processors do anyway.

Or has CS moved on since then??

Cheers,

Alex.

---------------------------------------------------------------------
Sheffield Linux User's Group - http://www.sheflug.co.uk
To unsubscribe from this list send mail to
- <sheflug-request [at] vuw.ac.nz> - with the word 
 "unsubscribe" in the body of the message. 

  GNU the choice of a complete generation.